Conventionally, in a power metal insulator semiconductor field effect transistor (MISFET) which is one of the power semiconductor devices, a power MISFET using a silicon (Si) substrate (hereinafter, referred to as an Si power MISFET) has been a mainstream.
However, the power MISFET using a silicon carbide (SiC) substrate (hereinafter, referred to as an SiC substrate) (hereinafter, referred to as an SiC power MISFET) can achieve higher breakdown voltage and lower loss compared to the Si power MISFET. Therefore, the SiC power MISFET has drawn attention in the field of power saving or eco-friendly inverter technologies.
Compared to the Si power MISFET, the SiC power MISFET can achieve a lower ON resistance at the same breakdown voltage. This is because the dielectric breakdown electric field intensity of silicon carbide (SiC) is about seven times as large as that of silicon (Si), so that an epitaxial layer serving as a drift layer can be made thin. However, considering the original characteristics to be obtained from silicon carbide (SiC), it cannot be said that sufficient characteristics have been obtained, and further reduction of the ON resistance has been desired from the viewpoint of high efficient utilization of energy.
One of the problems to be solved for the ON resistance of the SiC power MISFET of a DMOS (Double diffused Metal Oxide Semiconductor) structure is a parasitic contact resistance on a contact surface between a source diffusion layer and a metal electrode, which is a unique problem in the SiC power MISFET. The contact resistance component occupies about 0.5 to 1 mΩcm2 in the ON resistance component. Although the On resistance depends on a rated breakdown voltage, it is about 2 to 5 mΩcm2 in the case of a breakdown voltage of 600 to 1000 V. Therefore, a ratio occupied by the contact resistance is 10% or more, and the resistance increase and variation cannot be ignored. In general, in order to reduce the contact resistance, a silicide layer is formed on an SiC substrate where a contact is formed. Furthermore, it is desirable that a substrate concentration of a contact surface between the silicide layer and the source diffusion layer is high, and a range of 1×1019 cm−3 to 1×1021 cm−3 is desirable.
Nitrogen or phosphorus is used as an impurity of the source diffusion layer in an SiC power DMOS (for example, Non-Patent Documents 1 and 2). In the case where the nitrogen is used as an impurity, there is a problem in that a solid-solubility limit is low and electrical activation is not sufficiently achieved even when the impurity is implanted at a high concentration. For example, as described in Non-Patent Document 1, even when phosphorus and nitrogen are implanted at the same concentration and an activation thermal treatment is performed at the same temperature for the same period, the nitrogen is less electrically activated, and sheet resistance in the case where nitrogen is used as an impurity is ten times higher compared to the case where phosphorus is used as an impurity.
Therefore, there is a need for a technology to use phosphorus in the source diffusion layer of the contact portion. For example, as described in Japanese Patent Application Laid-Open Publication No. 2006-173584 (Patent Document 1) and Japanese Patent Application Laid-Open Publication No. 2009-064970 (Patent Document 2), a method of using phosphorus as an impurity of the source diffusion layer of the contact portion is disclosed.